1. Technical Field of the Invention
This disclosure relates to a power detecting circuit of a semiconductor memory device, and in particular to a power detecting circuit having a power-on reset function and a power-on read function of a semiconductor memory device. Further disclosed is a method for generating a power-on reset signal and a power-on read signal.
2. Description of the Related Art
A semiconductor memory device includes an array of memory cells and a number of logic circuits for controlling the array. For example, the logic circuits may be formed of a number of latches and flip-flops. Logic circuits, and in particular, flip-flops and latches, must initially have states that are well-defined. This is accomplished by a power detecting circuit. A conventional power detecting circuit outputs a power-on reset signal that is activated during a predetermined interval of time until a power supply voltage reaches a predetermined voltage at power-on. The power-on reset signal is inactivated when the power supply voltage reaches the predetermined voltage. Logic circuits in a semiconductor memory device are reset to their initial states at activation of the power-on reset signal.
In the case where non-volatile memory devices are used as a boot-up memory, a read operation is carried out after a power-on reset operation is performed. A voltage detecting circuit is used that detects a power supply voltage and switches the logic state of its output signal when the power supply voltage reaches a predetermined voltage (i.e., a detection voltage). For example, if a power supply voltage reaches a detection voltage, an output signal of a power detecting circuit has a high-to-low transition, and a read operation commences when the signal transition is received by the memory chip. However, noise may be caused by an unstable state of an external power supply voltage or excessive power consumption in the chip. If this occurs, the chip power supply voltage may be suddenly lowered below the detection voltage. If the power supply voltage falls below the detection voltage, it may be raised up to the power supply voltage again. In this case, a voltage detecting circuit detects variation of a power supply voltage, and an output signal of the detecting circuit has a high-to-low transition according to a detection result. This causes the read operation to commence, even though the system was not in a power-up phase. Since low-voltage memory devices are very sensitive to noise, problems such as this abnormal read operation may become more serious.
Accordingly, a memory device capable of preventing an abnormal read operation due to noise and a power detecting circuit having improved immunity is desirable.